1. Field
Embodiments relate to semiconductor memory devices and, more particularly, to a test mode control circuit in a semiconductor memory device and a test mode entering method thereof.
2. Description of the Related Art
In a process of fabricating a semiconductor memory device such as a dynamic random access memory (DRAM), the operation of a memory is checked by various tests to guarantee reliability of a product. These tests include an acceleration test performed by applying a high voltage in a high temperature ambient to remove an initial defect and a multi-bit test performed in the unit of a plurality of parallel bits to perform high-speed detection of whether there is a defect in function of a memory cell.
When these tests are conducted, a semiconductor memory device may receive a mode register set command such that a specific operation is performed to improve test efficiency. The specific operation is performed by setting a test mode. The tests are conducted before shipping products and used not by a user but by a semiconductor manufacturing maker. Although an entering condition of the test mode can be accidentally satisfied by a signal noise or mistake while in a user mode, satisfaction of the entering condition of the test mode during a user mode is an unintentional operation mode. There is a need for a more reliable entering condition for entering the test mode.